1. Field of the Invention
The present invention generally relates to computer chip manufacture and more particularly to dynamic random access memory cells for the 1 Gbit arena.
2. Background Description
In the migration to the 1 Gbit generation, the dynamic random access memory (DRAM) cells start to pass the 8 square (4.times.2 lithographic features) folded bit-line architecture limits. As illustrated in FIG. 1, predictions show that the one Gbit memory cell will be approximately a six square (3.times.2 lithographic features) cell. As can be seen in FIG. 1, solid line 1 represents the 8 square cell. As cell area requirements are decreased, the 8 square cell will be too large to meet density requirements for the number of chips on a wafer and too large to fit on a standard package.
One design is the merged isolation node trench (MINT) DRAM cell. As discussed in L. Nesbit et al. "A 0.6 .mu.m.sup.2 256Mb Trench DRAM Cell with Self-Aligned buried strap (BEST)," proceedings of the 1993 IEEE International Electron Devices Meeting; Technical Digest-International Electron Devices Meeting, 1993, pp. 627-630, the DRAM cell has shallow trench isolation (STI) constructed between adjacent trench capacitor cells. In this DRAM trench cell the transfer device region is bounded by shallow trench isolation oxide. The problem with the MINT cell design is the linear nature of the cell. All the active elements are ordered in a straight line. This gives the cell advantage over other designs in the way the cell responds to overlays of various masking levels, but it makes it difficult to scale below 8 square. Space must be provided for bitline contact, transfer device, buried strap, deep trench and isolation. This is shown in the top view of FIG. 2, where cell length is represented by arrow 10. Bitline contact 11 and diffusion 12 are provided on either side of active wordline 13. Deep trenches 14 are within passing wordline 15. All structures are surrounded by STI 16.
In the 1 Gbit time frame, the industry needs to push past the 8 square limits to achieve manufacturable chip size targets.